This work presents an integer-N divider based on multi-modulus frequency dividers (MMDs) which covers a continuous integer-N divider ratio range of 8 to 127 and was built using current mode logic (CML). A new powerful and simple modulus extension for MMDs optimized for fast CML implementations is demonstrated. The proposed divider is a hybrid composition of emitter coupled logic (ECL) stages and source coupled logic (SCL) stages. Along an input frequency range of 1 GHz to 7.5 GHz the needed input voltage level is less than 45 mVPP which is equivalent to -20 dBm at a 100Ω load. The maximum operating input frequency is 8.1 GHz while the divider consumes only 18.4 mW. The circuit was implemented in a low cost 180 nm BiCMOS process and is an essential part of a phase looked loop circuit (PLL). Together with the controllable current biasing circuitry it occupies an area of less than 0.09 mm2.